Complementary metal-oxide-semiconductor (CMOS) transistors in high performance integrated circuits require a low resistance electrical contact to the gate and source/drain regions of the transistors. In forming this contact, a silicide layer is first formed on the transistor gate and source/drain regions. A self aligned silicidation process (salicide) is often used to form the silicide layers. In this process, a blanket metal film is first deposited on the silicon substrate containing the MOS transistor structure. The metal is then reacted with the underlying silicon regions to form a low resistance metal silicide layer. Any un-reacted metal remaining on the substrate is then removed using a metal etch process that is selective to the metal silicide present. During this process it is critical that the metal silicide layer not penetrate into and/or through the underlying source/drain regions. Such metal silicide penetration, if it occurs, can lead to increased leakage currents rendering the integrated circuit inoperable.
Given its low resistivity and low temperature of formation (<400° C.), nickel silicide (NiSi) is increasingly being used to form the silicide layers in integrated circuits. Current methods of nickel silicide formation often results in an uneven nickel silicide semiconductor interface caused by spiking of nickel di-silicide (NiSi2) into the underlying semiconductor during formation. As described above, nickel disilicide spiking leads to increased transistor leakage currents and possible failed integrated circuits. There is therefore a need for a nickel silicide formation process that eliminates silicide spiking during formation.